#ifndef _TABLES_ENC_CTL_H
#define _TABLES_ENC_CTL_H
/*
 * Copyright 2011 Sylvain Bertrand (digital.ragnarok@gmail.com)
 * This fork is protected by the GNU affero GPLv3 with additionnal rights
 * Original code from Advanced Micro Devices, Inc.
 */

#define ENC_ACTION_DISABLE				0x00
#define ENC_ACTION_ENABLE				0x01
#define ENC_ACTION_DP_LINK_TRAINING_START		0x08
#define ENC_ACTION_DP_LINK_TRAINING_PATTERN1		0x09
#define ENC_ACTION_DP_LINK_TRAINING_PATTERN2		0x0a
#define ENC_ACTION_DP_LINK_TRAINING_PATTERN3		0x13
#define ENC_ACTION_DP_LINK_TRAINING_COMPLETE		0x0b
#define ENC_ACTION_DP_VIDEO_OFF				0x0c
#define ENC_ACTION_DP_VIDEO_ON				0x0d
#define ENC_ACTION_QUERY_DP_LINK_TRAINING_STATUS	0x0e
#define ENC_ACTION_SETUP				0x0f
#define ENC_ACTION_SETUP_PANEL_MODE			0x10

#define ENC_CFG_SEL_MASK		0x70
#define ENC_CFG_SEL_SHIFT		4
#define ENC_CFG_LINK_RATE_1_62_GHZ	0x0
#define ENC_CFG_LINK_RATE_2_7_GHZ	0x1
#define ENC_CFG_LINK_CATE_5_4_GHZ	0x2

#define ENC_BPC_UNDEFINE	0x00
#define ENC_6BITS_PER_COLOR	0x01 
#define ENC_8BITS_PER_COLOR	0x02
#define ENC_10BITS_PER_COLOR	0x03
#define ENC_12BITS_PER_COLOR	0x04
#define ENC_16BITS_PER_COLOR	0x05

struct enc_ctl_params {
	u16 pixel_clk;		/* in 10kHz unit */
	u8 cfg;			/* [7] rsvd
				   [6:4] encoder selection 0~5
				   [3:1] rsvd
				   [0] link rate
				     0: 1.62GHz
				     1: 2.7 GHz */
	u8 action;
	union {
		u8 mode;	/* 0: DP encoder
				   1: LVDS encoder
				   2: DVI  encoder
				   3: HDMI encoder
				   4: SDVO encoder
				   5: DP audio */
		u8 panel_mode;	/* valid when action
				   = ENC_ACTION_SETUP_PANEL_MODE
				   0: external DP
				   1: internal DP2
				   0x11: internal DP1 for NutMeg/Travis DP
				         translator */
	};
	u8 lanes_n;		/* how many lanes to enable */
	u8 bpc;			/* bit per color component, valid for DP mode
				   when action = ENCODER_ACTION_SETUP */
	u8 rsvd;
} __packed;
#endif
